Aug 13, 2020
Cadence Delivers Machine Learning-Optimized Xcelium Logic Simulation With up to 5X Faster Regressions
Mar 23, 2020
Synopsys Delivers Industry's First Ethernet 800G Verification IP for Next-Generation Networking and Communications Systems
Nov 19, 2019
Graphcore leveraged Mentor's Questa technologies to verify massive Colossus GC2 AI processor
Jun 19, 2019
Riviera-PRO™ Users to Benefit from Automatic UVM Register Generation Plus the Latest Verification Methodology Libraries
May 01, 2019
Synopsys Announces Industry's First DDR5 NVDIMM-P Verification IP for Next-generation Storage-class Memory Designs
Mar 14, 2019
Synopsys Delivers Industry's First USB4 Subsystem Verification Solution, VIP, and Test Suite for High-performance USB Architecture
Oct 11, 2018
Mentor's Questa verification solution helps Leonardo accelerate aerospace FPGA development
Aug 27, 2018
Synopsys Delivers 10X Performance in Formal Property Verification with Breakthrough Machine Learning Technology
Feb 26, 2018
AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports Cadence Perspec System Verifier using System Level Notation
Feb 26, 2018
AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports IEEE Standard 1801 and CPF Power-Intent Specification Formats
Oct 30, 2017
Media Alert: Connect, Share and Discuss the Latest Design and Verification Best Practices at the 2017 Cadence Jasper User Group Conference
Jun 15, 2017
Mentor Verification Is First to Deliver Portable Stimulus Technology Across the Full Enterprise Verification Platform